This is JFET sample and hold circuit. In this circuit, the logic voltage is applied simultaneously to the sample and hold JFETs. This is the figure of the circuit;
The errors due to rds (on) of the JFETs can be minimized by matching feedback capacitance and resistance and input impedance. The circuit performance is greatly improved because of matched leakage currents of the FM1109 monolithic dual and the inherent matched rds (on). [Circuit Schematic Source: National Semiconductor Application Note]
The errors due to rds (on) of the JFETs can be minimized by matching feedback capacitance and resistance and input impedance. The circuit performance is greatly improved because of matched leakage currents of the FM1109 monolithic dual and the inherent matched rds (on). [Circuit Schematic Source: National Semiconductor Application Note]
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