This is a circuit for testing the time. This circuit is built using JFET. This is the simple form. Here’s the schematic circuit diagram of the time test circuit.
Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = −5. The FET used to isolate the probe capacitance. The output = 10V step. AV = −5 for LF357. [Schematic source: National Semiconductor, Inc].
Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = −5. The FET used to isolate the probe capacitance. The output = 10V step. AV = −5 for LF357. [Schematic source: National Semiconductor, Inc].
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